Embodiments of the present invention relate generally to a metal-insulator-metal (referred to as “MIM” hereinafter) capacitor structure having high capacitance, and an integrated circuit chip including same.
This application claims the benefit of Korean Patent Application 2004-101183 filed on Dec. 3, 2004, the contents of which are hereby incorporated by reference.
Capacitors may be classified accordingly to their junction structure, for example, as metal-oxide-silicon (MOS), p-n junction, polysilicon-insulator-polysilicon (PIP), metal-insulator-metal (MIM), etc. All the above-mentioned examples, except MIM capacitors, comprise at least one electrode material formed from a mono-crystalline silicon or polycrystalline silicon material. However, this use of the mono-crystalline silicon or a polycrystalline silicon limits attempts to reduce the inherent electrical resistance of the constituent electrode. As a result, if a bias voltage is applied to the mono-crystalline silicon or polycrystalline silicon electrode, a depletion region may form, thereby destabilizing the voltage applied to the electrode. When this happens, the capacitance value of the capacitor is not uniformly maintained.
In contrast, the resistance of MIM capacitor electrodes may be additionally reduced, thereby making the capacitor less frequency dependent. Additionally, MIM capacitors have a good capacitance change rate in relation to variations in applied voltage and/or temperature.
As a result of these positive voltage capacitance and/or temperature coefficient characteristics, MIM capacitors are often used in analog products, products receiving mixed signal modes, and products based on system-on-chip (SOC) structures. For example, MIM capacitors are frequently used as an analog capacitor or a filter capacitor in analog or mixed mode signal applications, such as those found in cable/wireless communications. MIM capacitors are also frequently used as a decoupling capacitor on a main process unit board, or an RF capacitor in a high frequency circuit, such as those associated with an embedded DRAM.
FIG. (FIG.) 1 is a cross-sectional view illustrating a semiconductor device having a conventional trench-type MIM capacitor and related interconnections. Referring to FIG. 1, the MIM capacitor comprises a lower electrode 110a, a dielectric layer 130, a conductive layer 140a, and an upper electrode 150a. Also associated with the MIM capacitor structure are related interconnection layers, including lower interconnection 110b and upper interconnection 150b. 
Lower electrode 110a and a lower interconnection 110b, typically formed with the same thickness, are formed on a substrate 100. An interlayer insulating layer 120 is then formed on lower electrode 110a and lower interconnection 110b. An opening 125a is formed in interlayer insulating layer 120 to expose a portion of an upper surface of lower electrode 110a. Thereafter, dielectric layer 130 and conductive layer 140a are sequentially formed to predetermine thicknesses within opening 125a on the exposed portion of the upper surface of lower electrode 110a. Upper electrode 150a is then formed on conductive layer 140a. At the same time, upper interconnection 150b is formed on interlayer insulating layer 120.
Prior to the formation of upper interconnection 150b, a contact hole 125b is formed through interlayer insulating layer 120 to expose a portion of lower interconnection 110b. A contact plug 140b is formed to fill contact hole 125b, such that lower interconnection 110b is electrically connected to upper interconnection 150b. 
As can be seen from the illustrated conventional example, only a portion of the upper surface of lower electrode 110a (e.g., a laterally extending conductive surface) is used to form the capacitance structure of the MIM capacitor (i.e., to develop a capacitive charge). As lateral layout space in semiconductor devices comes at an increasing premium, this conventional arrangement suffers from real limits in a designer's ability to increase the overall capacitance of the MIM capacitor. Indeed, as emerging design rules mandate smaller MIM capacitors, the conventional design fails to provide sufficient capacitance.